Multiple Vth CMOS for Leakage Control in Deep Submicron IC's

Multiple-threshold CMOS circuit, which has both high and low threshold transistors in a single chip, can be used to deal with the leakage problem in low voltage low power (LVLP) and high performance applications. The high threshold transistors can suppress the subthreshold leakage current, while the low threshold transistors are used to achieve the high performance. In this paper, we will introduce some recently developed multiple-threshold CMOS circuit design techniques, such as multi-threshold-voltage CMOS (MTCMOS), variable threshold CMOS (VTCMOS), dynamic threshold CMOS (DTMOS), double gate dynamic threshold SOI CMOS (DGDTMOS) and dual threshold CMOS, etc. Dual threshold technique can reduce leakage power by assigning a high threshold voltage to some transistors in non-critical paths, and using low-threshold transistors in critical path(s). Therefore, both low power and high performance can be achieved simultaneously. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. Results show that dual threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, leakage power can be reduced by more than 80%. 1 Introduction With the growing use of portable and wireless electronic systems, reduction in power consumption has become more and more important in today's VLSI circuit and system designs 1], 2], 3]. For a CMOS circuit, total power includes dynamic and static components during the active mode of operation. It can be expressed as P T = P dyn + P leaka (1) where P dyn and P leaka are dynamic power and active leakage power. In standby mode, the power dissipation (P leaks) is due to the standby leakage current. Ignoring power dissipation due to direct-path short circuit current, dynamic power of a CMOS circuit is due to the charging and discharging of load capacitances, which can be evaluated as P dyn = 1 2 (X i2all nodes (i)C L (i))V 2 dd f clk (2) where C L (i) is the load capacitance, V dd is the supply voltage and f clk is the clock frequency. The leakage power of a CMOS circuit is determined by the leakage current through each transistor , which has two main sources: reversed-biased diode junction leakage current and subthreshold